description features 9-bit ideal for byte-parity applications flow-through configuration extra ttl and ecl power/ground pins to minimize switching noise ecl and ttl enable inputs dual supply 3.5ns max. d to q pnp ttl inputs for low loading choice of ecl compatibility: mecl 10kh (10hxxx) or 100k (100hxxx) fully compatible with motorola mc10h/100h600 available in 28-pin plcc package the sy10/100h600 are 9-bit, dual supply ttl-to-ecl translators. devices in the micrel-synergy 9-bit translator series utilize the 28-lead plcc for optimal power pinning, signal flow-through and electrical performance. the h600 features both ecl and ttl logic enable controls for maximum flexibility. the 10h version is compatible with mecl 10kh ecl logic levels. the 100h version is compatible with 100k levels. 9-bit ttl-to-ecl with ttl, ecl enable sy10h600 sy100h600 final block diagram rev.: d amendment: /0 issue date: february, 1998 pin configuration 18 17 16 15 14 13 12 q 8 q 7 v cco q 6 v ee q 5 q 4 567891011 26 27 28 1 2 3 4 top view plcc 25 24 23 22 21 20 19 v cct d 3 d 2 d 1 d 5 d 4 d 0 d 6 d 7 d 8 gnd enttl nc enecl q 0 q 1 v cce v cco q 2 v cco q 3 pin function gnd ttl ground (0v) v cce ecl v cc (0v) v cco ecl v cc (0v) ?outputs v cct ttl supply (+5.0v) v ee ecl supply (?.2/?.5v) d 0 ? 8 data inputs (ttl) q 0 ? 8 data outputs (ecl) enecl enable control (ecl) enttl enable control (ttl) pin names q 0 d 0 ttl ecl enecl enttl q 1 d 1 q 2 d 2 q 3 d 3 q 4 d 4 q 5 d 5 q 6 d 6 q 7 d 7 q 8 d 8 1
2 sy10h600 sy100h600 micrel logic diagram dc electrical characteristics v cct = 5.0v 10%; v ee = 4.75v to 5.5v (10h version); v ee = 4.2v to 5.5v (100h version) t a = 0 ct a = +25 ct a = +85 c symbol parameter min. max. min. max. min. max. unit condition i ee power supply current, ma ecl 10h 125 125 125 100h 122 123 132 i cch power supply current, 48 48 48 ma i ccl ttl 50 50 50 logic diagram ac electrical characteristics v cct = 5.0v 10%; v ee = 4.75v to 5.5v (10h version); v ee = 4.2v to 5.5v (100h version) t a = 0 ct a = +25 ct a = +85 c symbol parameter min. max. min. max. min. max. unit condition t plh propagation delay to output ns 50 ? to 2.0v t phl d 1.4 3.0 1.5 3.2 1.7 3.5 enecl/enttl 1.8 3.7 1.9 3.9 2.0 4.1 t r output rise/fall time 0.5 1.5 0.5 1.5 0.5 1.5 ns 50 ? to 2.0v t f 20% to 80%, 80% to 20% logic diagram product ordering code ordering package operating code type range sy10h600jc j28-1 commercial sy10h600jctr j28-1 commercial sy100h600jc j28-1 commercial sy100h600jctr j28-1 commercial logic diagram truth table enecl enttl d q hxh h hxl l xhh h xhl l llx l
3 sy10h600 sy100h600 micrel 28 lead plcc (j28-1) rev. 03
4 sy10h600 sy100h600 micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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